Conventionally, semiconductor packaging is formed through layer by layer buildup on a central glass reinforced core material, as one option, to enable fine routing and act as a space transformer between the silicon and motherboard. This approach however may not provide sufficient routing density especially in cases where die split and very fine routing between both die are needed. Alternatively, semiconductor packages can be formed through a coreless process in which the first layer is embedded, this will afford finer routing as it eliminates the need for seed layer removal (improve on compensation). These 2 approaches formed through organic substrates are generally trying to compete with silicon interposers and organic interposers that make use of “fab-like” processes—using seed layer sputter, thin liquid resist and forming thin copper routing layer. This provides very fine routing but the cost and the Cu thickness, and consequently electrical resistivity are major drawbacks. Accordingly, there are long-felt industry needs for methods that improve upon conventional methods including the improved methods and apparatus provided hereby.
The inventive features that are characteristic of the teachings, together with further objects and advantages, are better understood from the detailed description and the accompanying figures. Each of the figures is provided for the purpose of illustration and description only, and does not limit the present teachings.